High-Performance Co-Processing Architecture Using SOT-MRAM-Based In-memory Computing Scheme

In recent years, the rapid advancement of processor performance has highlighted the increasing inadequacy of memory bandwidth. To mitigate this challenge, the In-memory Computing (IMC) architecture has been proposed. Among various IMC implementations, Spin-Orbit Torque Random Access Memory (SOT-MRAM) stands out as an ideal generic co-processor due to its high density and low leakage current. However, how to efficiently integrate with existing instruction set architectures (ISA) while satisfying the characteristics of the SOT-MRAM IMC hardware poses a challenge. In this work, an instruction-driven in-memory co-processor architecture is proposed. By combining the proposed hardware-software collaborative memory redirection scheme, the SOT-MRAM-based in-memory computing can be merged into the existing computing architecture without disturbing ISA. Further, to satisfy the inter-row operation computation characteristics of SOT-MRAM IMC, a data pre-scheduling scheme oriented to efficient computation is proposed. Experimental results demonstrate a 6.2x speedup and 64% power reduction compared to a CPU-only architecture, and a 28% improvement in acceleration ratio over the state-of-the-art IMC architecture.