A digital dynamic power monitor based adaptive clocking system for voltage droop mitigation in 5nm mobile application processor

High frequency supply voltage droops make serious operating voltage shift and various reliability issue. For voltage droop mitigation, this paper propose novel on-chip digital dynamic power monitor (DDPM) and droop mitigation system. This dynamic power estimation method use accurate linear regression based model by clock gating signals. In addition, we present a 5nm mobile processor integrates a digital dynamic power monitor based an adaptive clocking system. The DDPM predicts dynamic power per every clock cycle and find large di/dt using clock gating signals. Comparing to simulation, a mean error is less than 1.5%. Furthermore, the DDPM interfaces with a adaptive clock controller to dynamically change the clock frequency in response to large power slope, operating voltage of processor reduce max 31mV@0.9V (6.8% dynamic power reduction).