Sub-50-mV Static Flip-Flop Consisting of Recursive Stacking Body-Bias Logic Gates for Extremely Low-Voltage VLSIs

This paper presents an extremely low-voltage flip-flop (ELVFF) consisting of recursive stacking body-bias logic gates with the capability of operating at extremely low supply voltages. The ELVFF is based on a conventional NAND latch based flip-flop (NLFF), and consists of three-times-recursive-stacking body-bias NANDs (3RSBB-NANDs) and onetime-recursive-stacking body-bias inverters (1RSBB-INVs). The recursive-stacking and body-bias techniques provide an effective strategy for achieving ELV operation. The combination of these techniques allows for the enhancement of both the voltage gain and voltage swing of logic gates, thereby enabling the ELVFF to operate at extremely low supply voltages. Simulation results in a standard 180-nm CMOS process with a deep-n-well option indicated that our proposed ELVFF was capable of operating at an extremely low supply voltage of 40 mV. Measurement results also demonstrated that the ELVFF stored and maintained the correct logic with an amplitude of 27 mV and a power dissipation of 6.03 nW at a 39-mV power supply. The ELVFF is suitable for sub-100-mV ELV applications, such as energy harvesting, at the cost of an increased number of transistors, area, power, and delay time.