Impact of Variability Compensation on the Performance of an RRAM-based 3-SAT Solver

The impact of variability on the performance of an RRAM-Computing-in-Memory-based architecture solving 3-SAT unconstrained optimization problems is evaluated. Realistic CMOS variability parameters were extracted from a 28nm CMOS technology, while RRAM variability parameters were taken from measured devices reported in the literature. It is shown by extensive Monte Carlo simulations that a naïve implementation shows two different error characteristics with respect to (I) produce faulty solutions and (II) tendency for premature termination of iteration loops. A new variability compensation scheme is proposed, elaborated and evaluated for 3-SAT problems up to 200 variables and 860 clauses. By application of the proposed compensation scheme errors of type (I) and (II) are completely eliminated.