Performance Analysis of N-Type Stacked-Vertical FET for Enhanced in Advanced CMOS Applications

Novel stacked-VFET (VFETst) structure was proposed to overcome contact poly pitch scaling limitation. This study examined the DC/AC performance of VFET ${ }_{\text {ST }}$ for source-drain-source (SDS) and drain-source-drain (DSD) schemes. As a result, SDS outperformed DSD because of DC coupling by the low source potential. Although RC delay was slightly degraded by 11.5 % in SDS compared to VFETs with lateral connection, SDS achieved a significant 36.8 % area reduction. These results demonstrate the potential for next-node logic applications.