A Compound Timing Detection of Both Data Transition and Path Activation for Reliable In Situ Error Detection and Correction

Timing error detection and correction (EDAC) in resilient circuits helps eliminate excess timing margins. However, it faces misdetection risks when critical paths (CPs) remain inactive. We propose a 15-transistor timing error and path-activation detector (TEPD) capable of detecting both timing violations in late-arriving signals and CP activation, with robust operation down to 0.33 V. Regarding circuit-level error correction, we introduce an error-correcting flip-flop (ECFF), leveraging time-borrowing for zero-cycle response latency without requiring pipeline refresh. The custom-optimized ECFF adds only six transistors, increasing delay, dynamic power, and static power by 15%, 11%, and 14%, respectively, compared with a standard flip-flop, ensuring efficient error correction with minimal cost. A system-level voltage tuning strategy is further developed to handle continuous timing errors, ensuring robust adaptive voltage scaling (AVS) operation. Implemented on a neural network (NN) accelerator in the 28-nm CMOS, the system operates across a wide voltage range from 0.54 to 0.9 V. It achieves up to 52% power gain or 123% frequency gain at the near-threshold region, with negligible area and power overhead compared with the margined baseline.