Demonstration of a Hybrid Wiring Layer Assembly for Low-Cost sub-10μm Pitch Integration

The relentless drive toward miniaturization in electronic devices demands advanced interconnect technologies that support fine-pitch integration at low cost with uncompromised reliability. Hybrid wiring architectures are a potential approach that merge organic wiring layers with coarse pitches fabricated using semi-additive processes on organic polymers, with inorganic wiring layers with finer pitches fabricated using damascene processes in oxide materials. Prior work showed for the first time the feasibility of a damascene process on inorganic layers deposited on build up films, as well as solder-less, `Cu-Cu thermocompression bonding of dies at ${\leqslant} {10}$ μm pitch to the substrate. Despite their potential, the reliability and mechanical robustness of these hybrid substrates/assemblies under operational stresses is not fully understood, posing a barrier to their widespread adoption. In this work, we successfully demonstrate a hybrid wiring layer substrate with traces of 7 μm line and 3 μm space in ABF-GL102 and 5μm vias in low temperature ICPCVD oxide. Furthermore, dies were assembled at ${\leq} {10}\ {\mu}{m}$ pitch using a solderless Cu-Cu thermocompression bonding scheme utilizing a newly developed low temperature anneal at 240°C to improve electrical contact and mechanical robustness without exceeding the thermal budget of the hybrid substrate. A shear-force of 78.14 N was achieved which is greater than 3x MIL-SPEC for a 4 mm² die. Finally, the substrate underwent UHAST at 130°C and 85% RH for 96 hours with a minimal increase in leakage current.