Die-to-Die Parallel Interface Optimization Utilizing Deca's Novel M-Series Gen-2 Fan-Out Technology

A short-reach die-to-die (D2D) parallel interface, such as UCI-e, is promising to meet the demanding bandwidth density requirements of high-performance computing (HPC) applications. The increase in bandwidth density is heavily dependent on the increase in I/O density, which can be constrained by die-shifting during the die-attach and molding processes for molded 2.5D configurations. Deca has developed a Gen-2 M-Series Fan-Out technology featuring a novel Adaptive Patterning technique that compensates for die-shift by adjusting the lithography pattern in real-time during the manufacturing process. This innovation enables significantly smaller I/O capture pads and therefore much higher I/O density. In this article, we present a signal integrity analysis using the Deca Gen-2 M-Series Fan-Out technology with a Marvell UCIe-like D2D interface and compare it with another industry-standard technology. A wiring strategy for D2D routing is discussed, followed by signal integrity simulations in both the frequency- and time-domains. The results indicate that the Deca M-Series achieves similar signal integrity performance to the industry-standard solution, with insertion loss ranging from 0.7 to 0.9 dB at the frequency of interest, return loss better than −10 dB, and comparable eye diagram characteristics. Additionally, the impact of stacked vias and the optimization of the redistribution layer (RDL) stackup for parallel D2D interface are studied.