M-Series Fan-Out Interposer Technology (MFIT) – Scaling Up for HPC & AI

Exponentially increasing demand for die-to-die bandwidth has become the defining challenge of the chiplet era, driving innovations in both vertical and lateral interconnect technology. To scale beyond the practical limits of silicon interposers ($>2,500 \text{mm}^{2}$), flagship products are adopting fan-out interposers with embedded bridge die, passives, and other components. M-Series Fan-Out Interposer Technology (MFIT) offers a compelling platform for large-scale chiplet integration, including HBM3e and UCIe Advanced. Maskless laser direct imaging (LDI) lithography enables large area RDLs without reticle stitching. A new Adaptive Patterning technique, Adaptive Pad Stacks, maintains a robust process window for die placement when scaling to fine pitches and dozens of embedded bridges, e.g. $\pm 40 \mu \mathrm{m}, \pm 0.4^{\circ}$ for $45 \mu \mathrm{m}$ pitch and $\pm 15 \mu \mathrm{m}, \pm 0.1^{\circ}$ for $25 \mu \mathrm{m}$ pitch. Signal integrity analyses performed for UCIe Advanced at up to 32 Gbps and HBM3e at up to 9.6 Gbps meet all requirements. Power integrity analyses show the benefits of thick copper planes in embedded RDL bridges and on the fan-out interposer itself for demanding power distribution networks (PDNs) like HBM3e. Strategically placed embedded silicon capacitors enabled meeting PDN specifications without TSVs in the bridge die. Moreover, the re-usable RDL bridge designs simplify and speed-up product development.