Improving the Quality and Yield Performance of Vacuum Fluxless Reflow Soldering for High Density AI Chips

Based on bump composition and structure as well as the reflow process used, various defects such as wicking, voids, poor wetting, flaking, crack, surface roughness, and intermetallic compound (IMC) formation [1] can be observed related to under/over reflow, under-soak, or process controls. Using micro bumps with a pitch of 15 μm or less, we established a specific process window that yielded defect-free bump reflow with minimized IMC. This optimized process, verified through optical, scanning electron, and automated optical inspection (AOI), consistently produces defect-free bumps and ensures reliable reflow performance to meet high volume production requirements for high density AI chips. This approach benefits from existing copper pillar structures and offers opportunities for equipment suppliers to develop new solutions [2]. This paper explores the challenges and requirements of fine-pitch micro bumps, examining factors like system settings, surface appearance, and digital processing techniques.