Enabling $10 \mu ~\mathrm{m}$ Die-to-Die Pad Pitch in Flexible Fan-Out with TrueAdapt™

Die-to-die (D2D) I/O (wiring) pitch is limited to about $40 \mu ~\mathrm{m}$ in most conventional CMOS packaging [1]. This is mainly limited by the constraints of the particular package fabrication schemes, such as silicon interposers, embedded silicon bridge technology, or fan-out-wafer-level-packaging (FOWLP). This pitch is especially difficult to achieve in flexible electronics where additional process challenges exist. Applying the traditional flexible printed circuit board (PCB) approach to flexible electronics limits the wiring pitch to what is achievable in PCBs (usually in the $150-200 \mu ~\mathrm{m}$ range). At UCLA CHIPS, fan-out-wafer-level-packaging has been successfully applied in fabricating a variety of integrated flexible hybrid electronic devices. The platform that we have developed is called FlexTrate^™ [2], which uses polydimethylsiloxane (PDMS) as the molding compound. PDMS is a completely biocompatible and highly flexible material, enabling biomedical and wearable applications. For example, we have previously developed a flexible s-EMG device [3], and a high pixel density microLED array [4] [5] on the FlexTrate^™ platform. Furthermore, we have also developed TrueAdapt^™ [6], a technology that enables the scaling down of pad pitches in FOWLP to about $10 \mu ~\mathrm{m}$, which we have incorporated into the FlexTrate^™ platform. In this work, we demonstrate dies connected at $10 \mu ~\mathrm{m}$ and $20 \mu ~\mathrm{m}$ I/O pad pitches in a flexible package for which we show connectivity even after bending at 5 mm bending radius.