Architecting the Thermal Dissipation and Power Delivery for Chiplet-Based Wafer-Scale Systems and Experimental Demonstration of Segmented Vertical Cooling for Silicon Dielets at 1 W/mm2 Power Density

We have analyzed several options for thermal dissipation and power delivery of wafer-scale systems. A twophase cooling unit was vertically integrated onto a silicon dielet. With a power density of $1 \mathrm{W} / \text{mm}^{2}$ to mimic the high-power compute dielets on wafer-scale systems, we demonstrate a vertical heat extraction system scalable up to 300-mm wafer diameters with the potential to go to higher power densities.