Growth of Nanovoids in Electroless Cu Layer of Micro-Via After Thermal Reliability Test

In this study, we carried out FEM simulation for stacked micro-via and STEM characterizations for the electroless plating Cu layer of $1^{\text {st}}$ micro-via. The 2D simulation results show that the stress that induces the micro-via failure tends to concentrate to the bottom of $1^{\text {st}}$ micro-via of the three-layer stacked micro-via structure under the thermal cycle test. STEM characterization shows the growth of nanovoids in an electroless Cu layer during the thermal 3000-cycle test in both Ni-added and Ni-free Cu plating processes.