Innovative Silicon Die Thinning and Edge Protection of Chip-to-Wafer Hybrid Bonded Wafer for High-Density Multi-Chip Stacking

For multi-chip stacking using Chip-to-Wafer (C2W) Hybrid Bonding (HB) technique, one prominent approach is Inter-Die Gap Filling (IDGF) method. A major challenge in IDGF flow is achieving cost-effective, crack-free planarization of the dielectric fill. Ensuring crack-free planarization requires the dielectric thickness to match or exceed the silicon die thickness. Although thinner silicon dies can lower planarization time and costs, their fragile nature complicates handling during assembly. This study presents a novel non-standard silicon Chemical Mechanical Planarization (CMP) process for C2W hybrid-bonded wafers. The novel CMP process enables precise die thinning, significantly reducing dielectric planarization costs while mitigating thin-die handling challenges. Custom-designed slurry additives and polishing pads effectively minimize die-edge rounding and chipping. Process conditions, slurry composition and CMP pads-were optimized to achieve high silicon removal rates with enhanced surface integrity. This approach offers a scalable solution to improve manufacturing efficiency and reliability in advanced multi-chip integration.