Through GaN Via for 3D Heterogeneous Strata Integration

The integration of GaN with Si has attracted significant attention for its potential to combine GaN's superior high voltage and high-frequency operation with Si's wellestablished, cost-effective, and scalable manufacturing platform, paving the way for next-generation high-performance, energyefficient electronic systems in power, RF, and data communication applications. This paper demonstrates a through-GaN/AIN strata via process that establishes vertical connectivity from the $\mathbf{C u} / \mathbf{S i O}_{\mathbf{2}}$ back-end-of-line (BEOL) atop a GaN-on-Si wafer, through the IIIV stacking and stress buffer layer, down to the underlying (111) Si wafer. Inductively coupled plasma reactive ion etching (ICP-RIE) is employed for precise via etching and smooth sidewalls and followed by Cu damascene metallization to provide uniform metal filling and low-resistance interconnects. A through-GaN strata daisy chain test structure is designed to evaluate the electrical connectivity, enabling verification of via integrity and its connection to the underlying Si wafer. In this work, the throughstrata vias achieve a minimum dimension of $2 \mu \mathrm{m}$ in diameter with a $5 \mu \mathrm{m}$ pitch, enabling compact and scalable integration for power applications. The successful demonstration of electrical connectivity verifies the feasibility of this process. Furthermore, the through-GaN-strata via is compatible with the existing Si-IF fabrication process, making 3D heterogeneous layer stacking a promising approach for integrating dielets into advanced active substrates.