Electroplated In–In Flip-Chip Interconnection for Superconducting Quantum Application

Scalable and modular chiplet system integration is promising to be an important technology for future superconducting quantum processors, and thus, high-quality interconnect between chips poses high importance. In this work, a two-step In electroplating technique is utilized to fabricate interchip bumps on high-resistivity silicon and AF32 eco glass substrates. Due to the softness and ductility of In, bumps can be flip-chip bonded at R.T. with 180-s bonding time and no need for pretreatment or reducing atmosphere. This is very beneficial for quantum use since the performance of Josephson junction is sensitive to high temperature and etching process. Comprehensive nondestructive tests (including confocal microscopy inspection, X-ray inspection, and sealing ring hermeticity test) and destructive tests (including SEM, focused ion beam (FIB), electron backscattering diffraction (EBSD), and shear strength test) have been conducted. Furthermore, test vehicles connected by In bumps are fabricated to measure the electrical performance. For dc resistance, bump chain exhibits excellent linear ohmic characteristics at R.T., with a resistance drop near 3.6 K during the cooling process using the physical property measurement system (PPMS), indicating the trend of superconducting transition of In bumps. In the commonly used frequency region for superconducting quantum measurement and control, the ${S} _{{21}}$ parameters of reference coplanar waveguide (CPW) and bonded CPW on Si and AF32 eco glass are investigated. The ${S} _{{21}}$ loss is found to be basically <1 dB within 10 MHz–10 GHz, demonstrating the feasibility of In bumps for high-frequency signal transporting. Thus, this two-step In bump electroplating technique is promising to provide support for future scalable superconducting quantum chiplet architecture.