Optimization Heuristics for Grid-based Integer Linear Programming Package Substrate Router

With the increasing number of I/O pins in highly integrated semiconductor products, semiconductor packaging has become an essential yet complex part of integrated circuit (IC) design. The substrate plays an important role in advanced semiconductor packaging and provides the chip with electrical connections and heat dissipation. While numerous studies have addressed the substrate routing problem, only one state-of-the-art work provides a customized routing flow specifically designed for packages with wire-bonding style and fine-pitch ball grid arrays (FBGA), which are more widely used than advanced packaging due to their maturity and lower cost. However, the existing router suffers from unsatisfactory routability due to its simplistic implementation and lack of necessary consideration for finger connections. Therefore, this paper proposes several optimization heuristics, such as finger accessibility enhancement, progressive rerouting, and half-grid rerouting techniques, to further improve the overall routing completion rate. Experimental results show that the proposed heuristics are capable of avoiding routing resource wastage, achieving better routing quality, and eliminating design-rule violations.