Investigation of Degradation and Failure Mechanism in 1200-V Planar SiC MOSFET Under Statical Accelerated Lifetime Test

The rapid advancement of power electronics applications has propelled the development of SiC MOSFETs while simultaneously posing challenges to their long-term reliability. To address this, the reliability issues associated with long-term stress are comprehensively explored through Accelerated Life Tests’ (ALTs’) verification protocols, aiming to optimize devices and enhance experimental methodologies. 16 sets of ALT experiments were conducted under maximum Tj conditions for HTGB, HTRB, and H3TRB tests, divided into groups around rated voltage conditions. The correlation between stress and degradation is examined by comparing offline data at both 25°C and 175°C. In HTRB tests, precursors of failures are confirmed with further investigation into failure modes. For HTGB experiments, the degradation in the gate oxide under gate bias is characterized using the Tj-Vth and C-V methods. Additionally, the device failures due to HV-H3TRB are analyzed by electrical measurement and acoustic scanning. The experimental findings provide insights that inform the design of subsequent ALT experiments.