Mapping Self-Timed Sequential Circuits on the Basis of the Original Synchronous Counterpart Description

Self-timed (ST) digital circuits, which constitute a subclass of asynchronous circuits, have a number of advantages over synchronous and asynchronous counterparts. Due to the two-phase discipline, redundant data encoding and mandatory acknowledging of successful switching completion in each operation phase, ST circuits operate in a wider range of supply voltage and temperature and are more resistant to soft errors. Excessive hardware costs inherent in ST circuits do not play a significant role at the current semiconductor technology development level. However, the lack of qualified developers and automated design tools for ST circuits hamper the wide ST circuits' practical use. The paper considers an approach to the ST circuit design based on the formalized transformation of the original synchronous Verilog-description of a digital circuit into a description of an ST circuit that has all the ST circuit's properties and ensures the ST circuit synthesis with minimal hardware complexity. The most difficult stage of converting a synchronous circuit description into its ST description is sequential unit implementation. It requires taking into account the nuances of the functioning of ST triggers and units based on them. The paper proposes a formalized method for substituting ready-made parameterized templates of typical sequential ST units instead of synchronous counterparts based on extracting the synchronous counterpart's properties and selecting the most suitable ST template.