A Multi-High-Rate Structured Algebraic QC-LDPC Code for 3D TLC NAND Flash Memory

As the number of stacked layers in 3D NAND flash memory increases, the channels experience more complex noise, leading to significant fluctuations in the error detection rate. Error-correcting codes with varying error correction capabilities (ECC) are required at different flash stages. To address this issue, we investigate multi-high-rate low-density parity-check (LDPC) codes for 3D NAND flash memory in this paper. Firstly, we mathematically model the 3D triple-level cell (TLC) NAND flash channel based on the obtained data from the test platform. Then we propose a multi-high-rate structured algebraic quasi-cyclic LDPC (MHR-SA-QC-LDPC) code. Specifically, the MHR-SA-QC-LDPC code contains the fixed number of information bits and can be adjusted to various rates according to the characteristics of NAND flash channels. Both additive and multiplicative group construction methods are analyzed in the prime field. Simulation results demonstrate that the proposed LDPC codes outperform existing benchmarks in 3D TLC NAND flash channels, improving both ECC performance and device lifetime.