Crossed Bit Line (CBL) Architecture in 3D Flash Memory CMOS Directly Bonded to Array (CBA) Structure

In order to achieve cost-effective giga-byte storage with improved reliability and performance, this paper introduces Crossed BL (CBL) architecture (CBLA) in 3D Flash memory with CMOS directly bonded to array (CBA) structure. The CBLA allows for a reduction in staircase length without being constrained by the total WL switch (WLSW) length, resulting in a 12% chip size reduction for BiCS FLASH™ generation 8 (BiCS8) chips. Additionally, CBLA offers advantages such as avoiding the need to increase block size, reducing chip length in the x-direction, and maintaining ease of circuit placement. However, the implementation of CBLA narrowed the Sense Amp (S/A) X-pitch, which decreased the number of wiring tracks in the S/A and caused issues with the sense operation. These issues were successfully resolved by introducing the Local CLK method. Furthermore, the introduction of On-Pitch Select-Gate-Drain (OPS) technology not only reduces the memory array size by 15% in BiCS8 but also enhances performance.