Comparison and Performance Analysis of Parallel PMOS Load VCO with Other Conventional VCO Architectures

This paper presents a comparative analysis of five voltage-controlled oscillator (VCO) architectures: CMOS stage ring VCO, current starved VCO (CS-VCO), NMOS sink CSVCO, diode-connected PMOS load VCO, and the proposed parallel PMOS load VCO. The oscillator circuits were simulated using the Cadence Virtuoso platform. Based on the simulation results, the proposed architecture demonstrates superior performance, achieving a peak oscillation frequency of 29.48 GHz at 2V with a wide tuning range from 9.56 to 29.62 GHz, representing a tuning of 102.40% , while consuming only 1.12 mW of power. The proposed design's unique mechanism involves three inverting stages where the output from each stage is fed into an NMOS-only input of the next stage, significantly reducing input capacitance and increasing oscillation frequency. Additionally, its load includes two parallel PMOS configurations—a diode-connected PMOS load and a pseudo-NMOS load that acts as a current source. This parallel load enhances the operating point and tuning range by increasing current flow through additional parallel paths. Although it exhibits moderate phase noise (-55.79 dBc/Hz at 1 MHz offset), the architecture achieves an outstanding figure of merit (FoM) of -149.96 dBc/Hz, making it highly suitable for applications such as millimeter-wave communication systems, 5G transceivers, and RF front-end modules, where high frequency, broad tuning range, and low power consumption are prioritized.