Research on Parasitic Capacitance Reduction in All-Silicon High-Precision MEMS Accelerometers

Parasitic capacitances pose a critical challenge for high-precision capacitive MEMS accelerometer performance improvement, particularly for the sensitivity enhancement and self-noise minimization. For the sandwich structure MEMS accelerometer, glass top cap is commonly employed to reduce parasitic capacitances. However, considering the requirement for three-dimensional integration, an all-silicon structure is more appropriate for CMOS-MEMS integration. This study introduces a MEMS accelerometer with suspended electrodes based on low-resistivity silicon substrate. By minimizing the overlap area between the pickup electrode and the silicon substrate, the parasite capacitances are significantly reduced. Additionally, the relative motion induced capacitance change between the drive electrode and the substrate is shielded by the grounding electrode, which further mitigates the effect of parasitic capacitance on sensitivity. Experimental results demonstrate that parasitic capacitances decrease from 850 pF to 68 pF. The scale factor reaches 971 V/g, making almost 4.4 times improvement. Meanwhile, by decreasing the MEMS accelerometer resonant frequency, the self-noise finally reaches 0.9 ng/Hz^1/2, which is approximately equivalent to the thermodynamic noise of the device. These results validate the effectiveness of the proposed method, providing a solution for achieving low-parasitic capacitance in high-performance MEMS accelerometer design. [2025-0025]