A High-Performance Hardware Design for Polynomial Multiplication in the CRYSTALS-Kyber Algorithm

In the CRYSTALS-Kyber encryption algorithm, polynomial multiplication is one of the most time-consuming tasks, making the optimization of its hardware implementations crucial. In this paper, we propose a hardware architecture for polynomial multiplication in the CRYSTALS-Kyber encryption algorithm, including butterfly units for implementing numbertheoretic transform (NTT), inverse NTT (INTT), and point-wise multiplication (PWM) operations, as well as a conflict-free implementation for constant-geometry memory access on dualport memory. Unlike previous works that focus solely on optimizing NTT and INTT circuits, our approach also optimizes the PWM circuit. Experimental results show that our approach achieves excellent performance in terms of both clock frequency and chip area. Compared to hardware designs that use the same design parameters, our approach can achieve a smaller areatime product.