Proposal for Non-Volatilization of eFPGA Core

In the development of embedded FPGA (eFPGA), a novel programmable AND logic cell architecture termed programmable AND element (PAE) has been reported to reduce the configuration memory by approximately half while maintaining the same number of cells as a conventional look-up table (LUT), which is anticipated to reduce the area of eFPGA. Furthermore, the implementation of non-volatile technology in eFPGA is expected to contribute to expedited startups, reduced power consumption through minimal data transfer, enhanced reliability against unexpected power interruptions, and improved security for managing data within the chip. This non-volatile FPGA is particularly efficacious in environments where frequent access post-installation is challenging, such as embedded systems and network equipment. In this investigation, we rendered a PAEbased eFPGA non-volatile utilizing a 40 nm MTJ/CMOS hybrid process employing non-volatile Intellectual Property (NVIP) technology and evaluated the place-and-route (PnR) process, demonstrating that the eFPGA can be made non-volatile with an area approximately $1.5 \times$ that of a volatile eFPGA.