Throughput Enhancement for Dual-Bit/Cell Split-Gate Floating-Gate Flash Memory Cell with Non-Self Aligned Process Technology

This paper presents a throughput enhancement method for split-gate floating-gate (FG) NOR-type Dual-bit/cell (NORD) flash cell. It features a common select-gate (SG) and was integrated without using triple self-aligned process, that is, with non-self-aligned process (NSA). With an additional mask and photoetch, many process steps can be removed. In the end, we can save 20% process steps in the FEOL, which decreases 10% process steps in total. The total cost had been reduced by 1.8% even though with one additional photo-mask. The performance of this NSA-cell had been studied by TCAD and characterized by experiments and finally made a mass production at our 300-mm 90-nm node technology. Additionally, a novel cell structure was proposed to improve the NSA-cell. It shows a steady and comparable performance with SA-cell.