Circuit Model and Wordline Driver Targeting for Wordline Open Effect in 3D DRAM

From the reported 3D 1T1C DRAM memory architecture, WL to WL coupling is supposed to be very high especially when vertical pitch is shrunk continuously. Under this circumstance, the effect of WL open on array operation is investigated. The worst scenario of the array pattern is that the floating cell stores "0" under open WL and processing read "1" from its adjacent normal WL, which will induce read data error. A new sub-word line driver scheme is also proposed. In the pre-simulation, the WL coupling effect could be prohibited and the current read data is obtained finally.