VCD-CIM: A Vertical-Compute-Decode Digital Computing-In-Memory Area-Efficient Macro for Vector-Wise Computation With Variable Accumulation Length

Computing-In-Memory (CIM) has shown significant potential in handling inference tasks for edge artificial-intelligences (Edge-AI). However, as Edge-AI tasks grow increasingly complex and diverse, with a sharp increase in edge computing requirements and limited hardware resources, there is a pressing need for CIM designs customized for Edge-AI to improve both throughput and area efficiency. Nevertheless, Edge-AI tasks involve numerous vector-wise computations with variable accumulation lengths, which obstruct enhancements in CIM area efficiency. In this paper, we introduce a solution by proposing a vertical-compute-decode digital CIM architecture (VCD-CIM) featuring vertical compute units and a vertical-decode-adder-tree. This CIM architecture enables area-efficient full-precision data/vector-wise computations for Edge-AI inference tasks. Additionally, we employ a data-priority CIM strategy. In post-layout simulations, for signed 8-bit inputs, 8-bit weights, and 23-bit outputs, VCD-CIM achieves a peak energy efficiency of 30.11 TOPS/W and maintains an area energy efficiency of 1.785 TOPS/mm2 across the accumulation length range of 4 to 128. We validate the effectiveness of the VCD-CIM architecture through simulations on the MobileViT network, achieving CIM array activation rates between 75% and 100% during complete network inference tasks.