Efficient ALU Design using Reversible Logic Gates

The Arithmetic and Logical Unit (ALU) is a fundamental component of the Central Processing Unit (CPU), responsible for executing arithmetic and logic operations. This work introduces a novel ALU design utilizing, reversible logic gates. We focus on implementing various reversible logic gates, including CNOT, Fredkin, Peres, and Toffoli gates, using the DSCH 3.5 tool which in turn are employed to construct multiplexers which are then integrated to form a complete ALU. The proposed ALU models demonstrate significant reductions in latency and power consumption. To meet the requirements of different ALU designs, we have adapted the multiplexer using two distinct reversible logic gates. According to our findings, the first design, incorporating a Toffoli-based multiplexer, achieves a power consumption of 0.017 mW and a path delay of 0.146 ns. In contrast, the second design, utilizing a Peres-based multiplexer, exhibits a power consumption of 0.030 mW and a path delay of 0.158 ns. These results, as evidenced by the timing diagrams from our simulations, highlight the efficiency of the proposed models.