A 30 MHz high-speed analog/digital PLL in 2 mu m CMOS

An analog/digital approach to data clock recovery that allows the implementation of a quasi-digital phase-locked loop (PLL) with an effective local clock frequency of 1 GHz in 2- mu m CMOS is described. The large phase jumps normally associated with digital PLLs are avoided. The basic concept of the clock recovery system is shown. A long ring oscillator (32 stages in this example) is permanently frequency locked to a reference frequency at the data window rate. Since the dynamics of this loop do not affect phase acquisition or tracking, the design is noncritical. Each tap on the ring oscillator is used to latch data samples into one of the 32 latches, so at the end of one round trip (one bit time) 32 samples spaced one gate delay apart are stored in the 32 data latches. In 2- mu m technology this gives an effective sample rate of 1 GHz. In 1- mu m technology it is about 5 GHz. After subsequently being moved to a separate holding register, the bit pattern is evaluated to determine the location of valid transitions in the data window by means of digital transition detectors of complexity appropriate to the application.<>