Graphene-Based FPGA Design and Optimization at the 7nm FinFET Technology Node

Emerging graphene-based interconnects exhibit excellent conductivity, rendering them a promising alternative to traditional interconnect materials. The energy consumption and delay of field-programmable gate arrays (FPGAs) are significantly influenced by global routing, which presents a compelling opportunity for graphene interconnect technology. This study examines the potential benefits of replacing copper (Cu), the conventional interconnect material, with graphene. Three interconnect technologies are examined: Cu interconnects, improved graphene-capped Cu interconnects, and thick graphene. An interconnect/system co-design framework is designed to systematically evaluate their performance differences. Concerning graphene material-level parameters, our focus is on the impact of graphene contact resistance and mean-free-path on performance. Benchmark simulations indicate that graphene-based interconnects can enhance the energy-delay product of circuits by up to 32% in comparison to conventional Cu interconnects at the 7nm FinFET technology node.