Optimized Reliable Content Addressable Memory

Dynamic Random Access Memory (DRAM) scaling is becoming increasingly questionable in terms of reliability and at the same time efficient Error Control Coding (ECC) architectures are needed to solve data correctness problems without impacting system performance too severely. This paper proposes an optimized reliable Content Addressable Memory (CAM) architecture for DRAMs. The proposed architecture employs a slightly larger base circuit, resulting in a 2 % increase in area while reducing power consumption by 3.63%. Although in contrast with current systems, the proposed solution improves the reliability of DRAM and CAM without any loss of existing features.