A 10-Bit Successive Approximation Register Analog to Digital Converter Using VCO-Based Time-Domain Comparator

The successive approximation register (SAR) analog-to-digital converter (ADC) architecture is employed to achieve low power consumption, allowing it to operate at low supply voltage. A time-domain quantization architecture based on a time-domain comparator is combined to overcome the design bottlenecks caused by the reduced intrinsic gain of transistors, the increased process variation, and the decreased supply voltage in advanced processes. A voltage-to-time converter based on a voltage-controlled oscillator (VCO) is used, providing the benefits of circuit stability and low noise impact. This design can be further improved by adding an SR time amplifier to the output of VCO, allowing the phase difference to grow exponentially. Hence, a faster escape from the dead zone of the phase detector can be realized to resolve the issue between high resolution and high speed in traditional VCO comparators. To accommodate the output generated by the improved voltage-to-time converter, the operation mode of the phase detector is modified, enabling it to be applied to the new voltage-to-time converter output. This paper presents a 10-bit SAR ADC in TSMC 40nm process, with a conversion rate of 10MS/s, a supply voltage of 0.9V, power consumption of 57.9µW, an ENOB of 9.88 bits, an SFDR of 74.07dB, and a FoM of 6.14 fJ/conv.-step.