Inline Defect and Logic and Memory Diagnostic Net Path Overlap Analysis Method

Inline inspections on advanced nodes always face challenges in terms of sensitivity and nuisance rates. It is difficult to optimize inspection recipes and efficiently check results for strong yield correlation. Engineers need to obtain inspection results with defect images and classifications, then compare these with yield data for optimization [1], [2], [3]. Here we demonstrate an accurate method for setting up inspection areas and reviewing the relationship between defects and fail bins by overlapping defect locations and fail net paths. Inspection areas can be defined by High Volume Diagnostic fail net path and implemented in inspection equipment. We can overlap defect locations with diagnostic fail net paths to evaluate the hit rate of the captured defect. This method can assist defect engineers in setting up high sensitivity and low nuisance recipes easily, help optimally utilize FA resources and support product engineers in finding more accurate directions to improve yield. Overall, advanced manufacturing fabs can implement this method to achieve higher yields quickly.