Full Wafer Inspection for Voltage Contrast Systematic Defects Using High-Throughput Point Scan

A next generation system and methodology for high-throughput e-beam hot spot inspection is described. Rather than capturing images of each hot spot, just a single pixel centered on the signal node of each hot spot is collected and used to assess if the hot spot is defective or not. This innovation results in a very substantial savings in time per hot spot, and therefore a tremendous increase in throughput over previous generation hot spot inspection systems. Additional throughput improvement is gained by moving the stage continuously under the wafer, commonly referred to as continuous scan, as these individual pixels (aka points) are collected. Throughputs of 1 billion hot spots per hour are routinely achieved. The process for selecting hot spots for optimal scan speed and learning is explained. Back-end-of-line (BEOL) defects are binned based on unique path, allowing the source of primary defectivity to be statistically determined. Application of this system to a metal 2 missing-metal-fill defect issue affecting a recent Intel technology is described. By leveraging this system and split experiments involving progressively more stressed wafers, a 6 orders-of-magnitude drop in defectivity was accomplished relatively quickly preparing this technology for high-volume-manufacturing.