Design and Implementation of Asynchronous Counter Using Reversible Logic Gates

In the present work, a low-power, high-performance asynchronous counter is designed, implemented and simulated using reversible logic. This reversible logic gates such as Feynman, Fredkin and Sayem gate are designed using transmission gates. The Sayem gate is designed using Feynman and Fredkin, whereas T-Flipflop is designed using Sayem and Feynman gate. A combination of all these reversible logic gates is used to design an asynchronous counter. As energy efficiency becomes a crucial concern in contemporary digital systems, especially in mobile and embedded applications. Reversible logic reduces power consumption by preserving information and preventing bit erasure, in contrast to conventional CMOS circuits that experience power dissipation as a result of irreversible logic transitions. For reducing energy loss during processing, reversible logic presents a possible solution. To further improve energy economy, the design makes use of transmission gates in conjunction with reversible gates. The asynchronous counter is designed using Cadence Virtuoso 45 nm technology. The proposed asynchronous counter is assessed with an emphasis on important performance indicators like average power and clock-to-Q latency which is calculated using the EDA tool. The asynchronous counter designed using reversible logic consumes an average power of $16.6927 \mu \mathrm{W}$ and has clock-to-Q delay of 1.45022 ns. This circuit may be used in frequency divider in embedded systems.