Novel Technique to Minimize Edge Delay and Leakage Power in CMOS Adder Circuits Using 22nm Technology

Propagation delay, output noise margin, and leakage power have become the most challenging parameters in large-scale CMOS circuits. As CMOS technology scales down, all three parameters contribute significantly to performance. However, all reported methods for reducing leakage have one or more drawbacks, such as voltage level shifting, increased propagation delay, and limitations at high clock speeds in smaller scales. The proposed novel feedback-based technique maintains output voltage with reduced leakage power and minimized propagation delay. Basic CMOS logic gates show reduced propagation delay and leakage power compared to LECTOR logic, 1T, and 2T-based sleep transistors. Additionally, the proposed logic was applied to a 1-bit full adder circuit, demonstrating lower leakage power and reduced propagation delay compared to a standard circuit under 22 nm CMOS technology.