IC Backside Tamper Detection Using Impedance Sensing

The expansion of flip-chip technologies and lack of backside protection made integrated circuits (ICs) vulnerable to certain classes of physical attacks mounted from the IC’s backside, including laser-assisted probing, electromagnetic side-channel analysis, body biasing injection (BBI), and focused ion beam (FIB) editing. Existing countermeasures are expensive, incompatible with standard IC fabrication, and unsuitable for legacy systems such as field-programmable gate arrays (FPGAs), which are widely used in industrial and defense systems. In this paper, we demonstrate how impedance monitoring of the printed circuit board (PCB) and the IC package’s power distribution network (PDN) using on-chip circuit-based network analyzers can detect IC backside tampering. Our method is based on the fact that any attempt to expose the backside silicon substrate, such as the removal of the fan and heatsinks, or polishing it, leads to changes in the equivalent impedance of the package’s PDN, and hence scanning the package impedance will reveal if the package integrity has been violated. To validate our claims, we deployed an on-FPGA network analyzer on an AMD Zynq UltraScale+ MPSoC (16 nm), which is part of a multi-PCB system. We performed a series of backside tamper attacks, including the removal of cooling components and IC backside silicon milling/polishing, across different temperatures, and evaluated detection effectiveness leveraging the difference of means as the statistical metric.