SMART: High-Performance SAR ATR Through Model-Architecture Co-Design on FPGA

Synthetic Aperture Radar (SAR) Automatic Target Recognition (ATR) is a fundamental technique in remote-sensing image recognition. SAR ATR systems demand real-time performance and low power consumption, particularly when operating in resource-constrained environments such as small satellites. This paper presents SMART, a model-architecture co-design on FPGA to address the challenges of high latency, large memory footprint, and high power consumption in state-of-the-art SAR ATR models. Model design: We develop a compact CNN with integrated spatial, channel and cross attention mechanisms, optimized through a softmax-free attention approach and quantization for improved computational efficiency and reduced latency. Architecture design: We implement a customized FPGA accelerator with a streaming dataflow architecture using high-level synthesis (HLS) on the Xilinx Alveo U280 FPGA. The design optimizes the dataflow through parameterized hardware kernels for key operations. Experimental results on the widely used MSTAR (99.84%), SynthWakeSAR (94.85%) and GBSAR (99.92%) datasets, demonstrate that our model achieves superior classification accuracy. Our design delivers up to 29× lower latency and 66× higher energy efficiency compared to implementations on state-of-the-art CPU and GPU platforms.