A 20 kHz-BW 110.2 dB-DR Third-Order CT ΔΣ ADC for MEMS Acceleration Sensors

This article presents a 20 kHz bandwidth (BW) third-order continuous-time (CT) delta-sigma ( $\Delta \Sigma $ ) analog-to-digital converter (ADC) for sensor measurement applications. The CT $\Delta \Sigma $ ADC that attempts to accomplish a high dynamic range (DR >110 dB) requires a low input resistance to reduce in-band noise spectral density (NSD). To resolve the conflict between the low sampling rate ( ${f}_{\text {s}}$ ) and the burdensome integration capacitor scale, a capacitance-multiplication integrator is proposed and the capacitor scale can be reduced by 75%. To deal with the voltage reconstruction issue that the chopping encounters, an optimized three-terminal chopping is adopted to guarantee the suppression of the flicker noise and the integrating performance simultaneously. In addition, a virtual-ground-switched solution for the resistive digital-to-analog converter (RDAC) is introduced to reduce the adverse effects of the intersymbol interference (ISI) and the parasitic resistance in the reference path on the ADC nonlinearity. The prototype ADC is fabricated in 180-nm CMOS technology. With the oversampling ratio (OSR) being 125, the ADC achieves a 106.9-dB signal-to-noise and distortion ratio (SNDR) and 110.2 dB DR while consuming 3.8 mW at 1.8-V supply. It results in an SNDR-based Schreier figure of merit (FoM) of 174.1 dB and a DR-based FoM of 177.4 dB. The measurement results of an NEMS acceleration sensor using the proposed ADC show that the average noise floor is $36.1~\mu $ V/ $\surd $ Hz in the BW of 0.1–1.6 kHz.