Design of Area-Efficient Memristor-Based XOR and XNOR Gates

This paper presents the novel area-efficient and optimized hybrid XOR and XNOR gates designed using four MOSFETs (two NMOS and two PMOS transistors) and four memristors. This work employs the Yakopcic memristor model and $TSMC\ 180\ nm$ CMOS PDKs for MOSFETs to design the logic circuits. The logic function of the proposed XOR and XNOR gates are verified using LTSPICE, and the valid logic outputs are obtained for all the input combinations. The effectiveness of the proposed XOR and XNOR gates is validated by simulating a full adder and a 2-bit magnitude comparator using LTSPICE.