ETCIM: Error-Tolerant Digital CIM Processor With Redundancy-Free Hard Error Repair and Run-Time Soft Error Correction

Digital computing-in-memory (CIM) has demonstrated outstanding energy and area efficiency. Although digital CIM avoids errors along the in-memory computing path, it is indispensable to correct hard and soft errors in digital CIM’s SRAM cells like conventional SRAM for commercial products. Hard errors come from defects in chip fabrication. Soft errors result from bit flips in an SRAM cell during CIM computation, and cause multiply–accumulation (MAC) errors. However, traditional SRAM’s error correction scheme cannot be directly applied to digital CIM, which causes hardware overhead in hard error repair, and incompatibility and latency problems in soft error correction. To tackle the above challenges, we propose an error-tolerant digital CIM processor ETCIM with three corresponding features: 1) a fault-adaptive CIM initializer (FACI) and input feeder reduce the hard error repair overhead by up to 8.47× power and 18.16× area savings; 2) a blockwise error correction code (BW-ECC) CIM macro suits the digital CIM structure that integrates multiple weight blocks, and corrects soft MAC errors; and 3) a progressive cell error corrector (PCEC) hides soft cell error correction latency during computation, reducing the total latency by up to 96.8%. The fabricated ETCIM achieves a state-of-the-art energy efficiency with an error correction of 19.5 tera operations per second (TOPS)/W at INT8.