Fault-Tolerant Design Framework for Probabilistic-Bit (P-Bit) Systems: Proposal and Analysis

Probabilistic-bit (p-bit) systems are promising computational platforms due to their potential for high energy efficiency, particularly when implemented using stochastic elements like low energy-barrier nanomagnets that exploit inherent thermal stochasticity. However, these stochastic elements are susceptible to getting stuck to a given state or transitioning too slowly due to faults arising during fabrication, ageing or other operational issues. This paper examines the impact of such faults on p-bit systems using a subset of the MNIST handwritten dataset as a case study and shows degraded system functionality due to such faults. To address these challenges, we propose a methodology based on mutual information to evaluate the criticality of individual p-bits in a network for a given application, quantifying their influence on system accuracy. Using the proposed criticality score (CS), we identify the most impactful p-bits and employ them in guiding fault-tolerance strategies. Additionally, we introduce the design of testable p-bits to detect faults in critical p-bits, validated through SPICE simulations using 14nm HP-FinFET technology. To further enhance fault resilience, we propose isolatable and fault-tolerant p-bits that help tackle accuracy loss caused by stuck-at faults. While these designs incur area overhead due to additional transistors, we can use the criticality score to replace only the most essential p-bits with fault-tolerant p-bits, minimizing unnecessary overhead while achieving desired fault-tolerance levels. Thus, this work demonstrates a comprehensive framework to develop fault-tolerance capabilities in a p-bit system implemented using stochastic elements susceptible to stuck-at faults.