Impact of Interconnect on Ferroelectric FinFET-Based Logic-in-Memory Circuits at 3nm Technology Node

This study delves into the impact of interconnects on Ferroelectric Field-Effect Transistor (FeFET) devices, employing ferroelectric materials in the gate stack for non-volatile memory at the 3nm technology node. Specifically, the study investigates the impact of interconnect on Logic-in-Memory (LiM) circuits. As the impact of interconnect become more pronounced at sub-nanometer scales, they are known to have a significant influence on circuit characteristics beyond the intrinsic properties of the components. Leveraging a newly developed path-finding process-design-kit (PDK), encompassing FeFET characteristics and interconnect properties, we explored various circuit configurations such as full-adder (FA) and ternary content-addressable memory (TCAM). Our investigation revealed that FeFET-based LiM circuits offer advantages in area, propagation delay, and power consumption compared to traditional CMOS-based circuits. While interconnects still influence FeFET-based circuit characteristics, their impact is somewhat tempered in comparison. We meticulously quantified these impacts. The simulation of how the next generation of advanced interconnect processes can further enhance FeFET-based LiM circuit performance was conducted using the PDK. Through this analysis, we proposed guidelines for the layout design of future FeFET-based LiM circuits.