Tutorial: Fundamentals of Process Monitors for Signoff-Oriented Circuit Design

In advanced technology nodes, the process technology requires more than a year to reach maturity. To avoid costly iterations between design and foundry, thus impeding time-to-market, the final validation of circuit timing and power, known as chip signoff, should leverage on-chip process monitors to speed-up process learning. This tutorial introduces the relationship between process and signoff in terms of speed/leakage, voltage, temperature and aging. Then, the tutorial covers the different types of digital circuits, with a focus on the corresponding challenges, to monitor this relationship. Since signoff requires a statistical methodology, silicon big-data collection and analysis are described to provide feedback to the foundry and designers.