Tutorial: Error-Correcting Codes in 5G/NVM Applications

The growing needs of efficient data transmission and storage are driving information delivery technologies to new frontiers. Either in the new radio (NR) links of 5G communications, or in emerging non-volatile memories (NVMs) with continuously increasing capacity, error correcting codes (ECCs) are essential and crucial in maintaining the data correctness. In this tutorial, we will cover major concepts in ECC design and architecture, including multi-Gb/s LDPC-BC, energy-efficient LDPC-CC, and Polar/Turbo decoders that fulfill different requirements in various 5G scenarios. For NVM applications, we will introduce 1-error and 2-error correcting scheme with parallel architectures for NOR flash, as well as BCH and LDPC coding schemes for NAND/3D-NAND, to address low-latency and high-throughput solutions.