Tutorial: Extending Processor Cores for Machine Learning

Many low-cost, ultra-low-power applications require flexibility and cannot afford the large silicon budget of a specialized machine-learning/artificial-intelligence (ML/AI) accelerator. The tutorial will review the key ideas and approaches to extend the instruction-set architecture (ISA) and microarchitecture, as well as the digital design of processor cores to achieve high efficiency for ML. ISA extension examples (e.g. ARM's Helium and RISC-V extensions) will be analyzed, along with implementation challenges and solutions, drawing insights from various silicon-proven RISC-V cores.