Tutorial: Noise Simulation in Mixed-Signal SoCs

This tutorial presents an overview of integrated power and substrate noise simulation techniques to verify noise coupling in mixed analog-digital system-on-chip integration. The simulation captures: (1) background mechanisms, (2) power noise generation in digital portions of a chip, (3) substrate noise propagation in a whole die, and (4) noise interference with analog circuitry on the same chip. The models for chip-package-board interaction in power delivery networks and noise coupling in a silicon substrate will also be covered. A silicon example of an LTE-class receiver chain uses hardware-in-the-loop simulation (HILS) for quantifying the in-band spurs due to noise coupling and measuring their impact on system-level communication performance such as error vector magnitude (EVM) and data throughput.