Short Course: Device and Physical Design Considerations for Circuits in FinFET Technology

CMOS scaling remains economically lucrative with 7nm mobile SoCs commercialized since late 2018 and 5nm products imminently available. Modest feature-size reduction and process innovations optimized for logic and SRAM scaling continue to offer compelling node-to-node power, performance, area, and cost benefits. This talk provides an overview of the key process technology elements that have enabled the FinFET CMOS nodes and highlights the resulting technology impact on design.