Tutorial: SoC Design Methodology for Improved Robustness

A holistic approach to power and performance attainment for semi-custom SoC designs is required to properly optimize future generation devices. We will cover novel techniques which tie SoC development together from micro-architecture to design signoff using examples from production SoCs. We discuss SoC clocking structures, local vs. distributed dividers, real-world implementation of clock-gating and data-driven clock power reduction. This is tied to design signoff, specifically, margin and signoff corner requirements including use of statistical STA. We will discuss how to select process corners and the type of outlier circuits which must be comprehended. Other novel areas of SoC optimization are considered including repeater insertion and repeater circuits for low power, auto-extraction and use of regularity in place and route, and SRAM power optimization.